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Maximizing performance of microprocessor can be achieved by expanding the set of actuators that can be represented by both combinational and sequential circuits. The integration of a combinational multiplier into a single-cycle processor greatly increases the critical path of the processor, which causes a decrease in its overall performance. This problem can be solved by pipelining the multiplying unit, which is an appropriate solution due to the small proportion of multiplication operations in integer programs. In this work, a pipelined multiplier with subsequent integration into a single-cycle processor is considered. The multiplier is designed using the Wallace tree algorithm that refers to accelerated multiplication algorithms. The processor archi-tecture for the integration of the multiplier being developed is the open RISC-V architecture. To determine the critical path and the resources spent, the project was implemented for FPGAs, and metrics were taken based on the results of synthesis in Vivado CAD. The metric of average pro-gram execution time is used to evaluate processor performance. The study of this metric for dif-ferent depths of the multiplier pipeline, as well as for a different proportion of multiplication op-erations in the program, has allowed the determination of the performance gain provided by pipelining of the multiplier.

Key words: multiplier, pipelining, single-cycle processor, critical path, Wallace tree, average program execution time, FPGA
Published in: CIRCUIT ENGINEERING AND DESIGN
Bibliography link: For citationi: Shevtsov N., Khisamov V. T., Pereverzev A. L., Ternovoy N. E. Pipelining of the Wallace multiplier for a single-cycle processor with RISC-V architecture. Izv. vuzov. Elektronika = Proc. Univ. Electronics. 2025;30(3)313–323. (In Russ.). https://doi.org/10.24151/1561-5405-2025-30-3-313-323.

Nikita Shevtsov
National Research University of Electronic Technology (Russia, 124498, Moscow, Zelenograd, Shokin sq., 1); KNS GROUP LLC (Russia, 123376, Moscow, Rochdelskaya st., 15, bld. 15)

Vasil T. Khisamov
National Research University of Electronic Technology (Russia, 124498, Moscow, Zelenograd, Shokin sq., 1)

Nickolay E. Ternovoy
National Research University of Electronic Technology (Russia, 124498, Moscow, Zelenograd, Shokin sq., 1)

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Information about the publication

UDK: 004.3
Publication type: Scientific article
DOI: 10.24151/1561-5405-2025-30-3-313-323
RISC id: DIOHQE

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